1. Field of the Invention
The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer applied to frequency hopping system.
2. Description of the Prior Art
Transceivers in a wireless communications system utilize frequency synthesizers to generate carrier frequencies (central frequencies) of different frequency bands for wireless signal transmission and reception. Regarding the new generation of the ultra-wide-band (UWB) communications system, the system combines multi-band orthogonal frequency-division multiplexing (multi-band OFDM) and frequency hopping technologies. According to corresponding protocol specifications, such as IEEE 802.15.3a, UWB system includes five band groups, where a first band group has three bands. Each band has a bandwidth of 528 MHz and corresponding central frequencies are 3432 MHz, 3960 MHz and 4488 MHz. Multi-band OFDM adopts time-frequency interleaving to transmit and receive OFDM symbols, indicating that the UWB system alternately operates in one of the bands when each time a symbol is transmitted or received. According to the specifications, Each OFDM symbol length is 312.5 nano-seconds (ns), and a frequency hopping from band to band is smaller than 9.5 ns. Therefore, a frequency synthesizer applied to the UWB system must cover the bands with respect to the carrier frequencies and can finish a frequency hopping in 9.5 ns.
In typical frequency synthesizer design, the PLL transition time of switching one band to another depends on the PLL bandwidth. If the PLL band switching time is considered to be less than 9.5 ns, the PLL bandwidth is necessarily more than 100 MHz. In addition, for a typical stable PLL design, a reference frequency in the PLL has to be 10 times or more the PLL bandwidth. With the above-mentioned restrictions, the typical frequency synthesizer needs to use the reference frequency of over 1 GHz for the UWB specifications, resulting in high power consumption, high cost and unpractical design.
To deal with the PLL-transition-time issue, many development and research institutions publish various solutions. For example, ISSCC (International Solid State Circuits Conference) 2005 Sec 11.9 p. 216-218 discloses a frequency synthesizer employing three independent PLL circuits and VCOs to generate the foregoing carrier frequencies at 3432 MHz, 3960 MHz and 4488 MHz. Under the architecture, the frequency synthesizer eliminates waiting for the PLL transition time. However, it costs triple current consumption and chip area to use three independent PLL circuits simultaneously.
JSSC (IEEE Journal of Solid-State Circuits) 2005 Aug. p. 1671-1679 discloses a frequency synthesizer employing two independent PLLs and a multiplexer. The multiplexer is used for selecting a carrier frequency from one of the PLLs to output. While one PLL is ready to transceiver data, the other switches and settle its frequency and the multiplexer changes selection output every symbol period (312.5 ns). The operation is considered a pipeline operation allowing each PLL transition time to become 312.5 ns instead of 9.5 ns. However, pipeline operation of two PPLs stills consumes double power and area. Besides, each PLL and VCO thereof must cover three bands, increasing design complexity.
The simplest PLL architecture employs one PLL, one VCO, and a Single-Side-Band Mixer (SSB Mixer). Please refer to FIG. 1, which is a schematic diagram of a frequency synthesizer 10 according to the prior art. The frequency synthesizer 10 can generate the above-mentioned carrier frequencies of the bands and includes a VCO 11, a PLL circuit 12, a frequency divider 14, a SSB mixer 16 and a multiplexer 18. The VCO 11 and the PLL circuit 12 are used to generate an in-phase signal and a quadrature signal both having a frequency f1 at 3960 MHz. The in-phase signal and the quadrature signal are called I/Q signal hereinafter for brevity. The frequency divider 14 divides the frequency f1 by 7.5 to generate I/Q signals with frequency f2 at 528 MHz. The SSB mixer 16 multiplies frequencies f1 and f2 and generates two down-converted/up-converted frequencies at 3432 MHz and 4488 MHz, respectively. In addition, the SSB mixer 16 determines one of the generated frequencies of 3432 MHz and 4488 MHz to output as a frequency f3 according to a control signal SC1. The multiplexer 18 selects the output frequency f1 or the frequency f3 to output according to a control signal SC2. Although this architecture is very simple, uses only one VCO and one PLL; however, the dividing number of the frequency divider 14 is 7.5, not an even integer. This increases difficulty for the frequency divider 14 to generate the I/Q signal with phase difference of exactly 90 degrees, implying a need of a poly-phase filter to generate I/Q signals.
In addition, image-signal suppression ability is a main consideration for selection of SSB mixers. Strong image signal component may cause severe spur noise in transmitters and a low signal-to-noise ratio (SNR) in receivers. That is, the more ideal characteristic (identical signal amplitude and exactly 90-degree phase difference) the I/Q signal inputted to the SSB mixer has, the better image signal suppression the SSB mixer could achieve. This is well known in the art and the explanation thereof is omitted. However, it is difficult for the SSB mixer to have an ideal I/Q signal input when high-frequency applications, and an extra narrowband filter is demanded to filter out the image signal. A Q index is used to determine filter design difficulty, where the Q index is defined as a value of a desired signal after signal mixing over frequency difference of the desired signal and the image signal. For the SSB mixer 16 in FIG. 1, the Q index is obtained by an equation: (f1+f2)÷(2×f2)=4.25. The higher Q index indicates that the SSB mixer requires a high Q-factor narrowband filter to filter out the image signal. As is well known in the art, the narrowband filter having a high Q factor has better filtering ability but the design complexity is high. Therefore, how to design a frequency synthesizer with a demanded low Q index filter is also a main object.
Please refer to FIG. 2, which is a schematic diagram of a frequency synthesizer 20 according to the prior art. The frequency synthesizer 20 includes a VCO 200, a PLL circuit 210, frequency dividers 220 and 230, a multiplexer 240 and SSB mixers 250 and 260. In FIG. 2, the oscillating frequency of the VCO is 4.224 GHz and the frequencies inputted to the mixer 250 are 528 MHz and 264 MHz. As a result, the Q index of the mixer 250 is obtained by (528+264)÷(2×264)=1.5. As for the mixer 260, the input frequencies are 4224 MHz and 264 MHz, and thereby the Q index is obtained by (4224+264)/(2×264)=8. The Q index of the mixer 260 is so high that the narrowband filter is difficult to be implemented. Besides, the VCO 200 requires a poly phase filter (PPF) to generate I/Q signals.
To improve the high Q-index problem, US Application no. 2006/0183455A1 discloses a frequency synthesizer including a VCO, a plurality of frequency dividers, a PPF, a PLL circuit and a mixer. The VCO generates a frequency at 7920 MHz, and divides to the frequency divider generates frequencies at 3960 MHz and 528 MHz. The PPF is responsible for transforming the signal at a frequency of 528 MHz into I/Q signals, and the mixer then generates the desired carrier frequencies. In the architecture, the Q index of the mixer is 4, applicable for design. However, the frequency synthesizer requires the PPF for I/Q signal and the VCO to operate at 8 GHz.
As above, the primary objective is to design a frequency hopping synthesizer architecture with low complexity, low power consumption and small area occupation.